Metal-oxide-semiconductor field-effect transistors (MOSFETs) having a channel formed in strained semiconductor, for example, in strained silicon formed on relaxed Si1−xGex, can exhibit improved carrier mobility in comparison to traditional MOSFETs. To provide compatibility with traditional silicon-based fabrication equipment and methods, “virtual substrates,” which include a strained semiconductor, can be used in place of conventional silicon wafers.
Virtual substrates based on silicon (Si) and germanium (Ge) provide a platform for new generations of very large scale integration (VLSI) devices that exhibit enhanced performance in comparison to devices fabricated on bulk Si substrates. An important component of a SiGe virtual substrate is a layer of SiGe that has been relaxed to its equilibrium lattice constant (i.e., one that is larger than that of Si.)
The relaxed SiGe layer can be directly applied to a Si substrate (e.g., by wafer bonding or direct epitaxy), or atop a relaxed graded SiGe buffer layer in which the lattice constant of the SiGe material has been increased gradually over the thickness of the layer. The SiGe virtual substrate may also incorporate buried insulating layers, in the manner of a silicon-on-insulator (SOI) wafer.
To fabricate high-performance devices on these platforms, thin strained layers of semiconductors, such as Si, Ge, or SiGe, are grown on the relaxed SiGe virtual substrates. The resulting biaxial tensile or compressive strain alters the carrier mobilities in the grown layers, enabling the fabrication of high-speed and/or low-power-consumption devices.
One technique suitable for fabricating strained Si wafers can include the following steps:
1. Providing a silicon substrate that has been edge polished;
2. Epitaxially depositing a relaxed graded SiGe buffer layer to a final Ge composition on the silicon substrate;
3. Epitaxially depositing a relaxed Si1−xGex cap layer having a constant composition on the graded SiGe buffer layer;
4. Planarizing the Si1−xGex cap layer by, e.g., chemical mechanical polishing (CMP);
5. Epitaxially depositing a relaxed Si1−xGex regrowth layer having a constant composition on the planarized surface of the Si1−xGex cap layer; and
6. Epitaxially depositing a strained silicon layer on the Si1−xGex regrowth layer.
The deposition of the relaxed graded SiGe buffer layer enables engineering of the in-plane lattice constant of the SiGe cap layer (and therefore the amount of strain in the strained silicon layer), while reducing the introduction of dislocations. The lattice constant of SiGe is larger than that of Si, and is a function of the amount of Ge in the SiGe alloy.
As a lattice-mismatched layer (such as a SiGe layer on Si, or a Si channel layer on a relaxed SiGe layer) is deposited, the layer will initially be strained to match the in-plane lattice constant of the underlying silicon substrate. Above a certain critical thickness of the lattice-mismatched layer, however, misfit dislocations form at the layer interface. The layer can relax to its inherent lattice constant due to mismatch accommodation by the misfit dislocations.
The process of relaxation occurs through the formation of the misfit dislocations at the interface between two lattice-mismatched layers. The misfit dislocations accommodate the lattice mismatch at the interface. Moreover, misfit dislocations are associated with bulk lattice dislocations that extend from each end of a misfit dislocation (termed “threading dislocations”). A threading dislocation can rise through the crystal to reach a top surface of the wafer.
A structure that incorporates a compressively strained SiGe layer in tandem with a tensilely strained Si layer can provide enhanced electron and hole mobilities. In this “dual channel layer” structure, electron transport typically occurs within a surface tensilely strained Si channel and hole transport occurs within a compressively strained SiGe layer below the Si layer.
Complementary metal-oxide silicon (CMOS) circuit design is simplified if carrier mobilities are enhanced equally for both NMOS and PMOS devices. In conventional silicon-based devices, electron mobilities are approximately two times greater than hole mobilities. As noted, electron mobilities have been substantially increased with strained silicon. Methods for equally increasing hole and electron mobilities by forming dual-channel NMOS and PMOS devices on the same substrate are problematic, in part because of different surface strained-silicon thickness requirements for the two types of devices.
Moreover, SiGe-based substrates can increase the complexity of device fabrication. For example, the electronic defects and fast diffusion pathways that misfit dislocations can introduce into a substrate can be detrimental for device fabrication and performance. Also, for example, the concentration profile of a Si—SiGe interface can deteriorate due to diffusion that occurs during elevated temperature processing steps. Thus, for example, the desired hole mobility enhancement of a SiGe channel layer can be substantially less than theoretical predictions suggest.